For purposes of insuring the integrity of a voltage level corresponding to a logic-1 in a load connected to the output of a BiCMOS driver circuit, it is desirable to have logic-1 from the output of the driver near or above the supply voltage to the driver circuit. If this desired situation were to occur, better discrimination between logic-0 and logic-1 would be possible. Additionally, for the sake of switching speed or rather a fast response time, it is desirable to have a BiCMOS driver which has low input loading (low amount of current drawn by the input of the circuit). Furthermore, high output loading capability (capability of supplying high current to an output load) is desired. Unfortunately, prior art BiCMOS drivers have been unable to furnish low input loading together with high output loading capability and a logic-1, at their outputs, near or above the supply voltage of the driver circuit.
A more detailed explanation of the limitations and problems associated with the prior art follows below with references to the accompanying FIGS. 1, and 2.
A standard BiCMOS driver is shown in FIG. 1. A logic-0 (low voltage) at the input node, IN, produces a logic-1 at node A from CMOS inverter 2. NMOS transistors 4 and 6 and bipolar transistor 8 are turned off due to the logic-0 at input node, IN. Node A has a voltage potential of approximately Vcc, the circuit supply voltage. Pull-up bipolar transistor 10 turns on due to the Vcc voltage from node A at its base and thus delivers power to output node, OUT.
Switching speed of the BiCMOS driver, shown in FIG. 1, is dependent upon the size of PMOS transistor 16 of CMOS inverter 2. The larger PMOS transistor 16 is, the more charges required to charge up MOS capacitor capacitor 15 in PMOS transistor 16 and therefore, the more current required to charge up or discharge capacitor 15, i.e. the more input loading. Consequently, switching speed of the BiCMOS driver decreases with an increasing size of PMOS transistor 16 (assuming that MOS capacitor 15 in PMOS transistor 16 increases with the size of PMOS transistor 16). Therefore, in order to increase switching speed, input loading of MOS capacitor 15 within PMOS transistor 16, should be decreased and consequently the size of PMOS transistor 16 should be decreased. However, since the pull-up speed of bipolar transistor 10 directly affects the switching speed of the BiCMOS driver, a large PMOS transistor 16 is required to quickly supply enough power to the base of bipolar transistor 10 so that it can quickly pull up the voltage at output node OUT. Therefore, in the prior art, maximum switching speed of the BiCMOS driver could not be attained due to constraints on the size of PMOS transistor 16 and base loading requirements of bipolar transistor 10.
High output loading capability is determined by the size of pull-up bipolar transistor 10. A high output loading capability is desired since increased output loading capability necessarily implies the ability to drive a larger load at the output and/or increased fan-out (fan-out being the maximum number of lines that can be driven by an output line) from node OUT. Pull-up bipolar transistor 10 must be large in order to provide enough current to output node OUT so that high output loading is possible. This further adds a constraint on PMOS transistor 16's size in that PMOS transistor 16 must be large in order to drive pull-up bipolar transistor 10. Large PMOS transistor 16 creates a low resistance path to Vcc during times it is turned on (input node IN at logic-0) to prevent the base of the pull-up, node A, from booting (rising) significantly higher than Vcc. Since the resistance associated with PMOS transistor 16 is small, the RC time constant associated with parasitic capacitor 12 is relatively small. Charge leaks off the plate connected to node A of parasitic capacitor 12 too quickly to enable it to boot (raise) node -A significantly past Vcc. Thus, the output node of the BiCMOS driver, node OUT, is only pulled up to approximately Vcc-Vbe. A timing diagram for the circuit in FIG. 1 is shown in FIG. 2. As shown in FIG. 2 a high output loading along with a maximally high voltage level corresponding to logic-1 could not be attained by the prior art.